Master-Slave JK Flip-Flop
A Master-Slave JK FF is two JK latches in series. The Master captures J/K on CLK = 1 (HIGH). The Slave transfers Master's output to Q on CLK = 0 (LOW). This two-phase capture eliminates the race-around condition.
Master-Slave JK — Two-Stage Design
Characteristic Table
| J | K | Q(t+1) | Operation |
|---|---|---|---|
| 0 | 0 | Q(t) | No Change ↗ |
| 0 | 1 | 0 | Reset ↓ |
| 1 | 0 | 1 | Set ↑ |
| 1 | 1 | Q'(t) | Toggle ⚡ |
Clock Cycle
State History
| J | K | Q(t) | Qm | Q(t+1) | Op |
|---|---|---|---|---|---|
| — Press CLK ↑↓ to begin — | |||||
How It Works
Why Master-Slave?
In a simple JK FF with J=K=1, if CLK stays HIGH for a long time, the output can toggle multiple times in one cycle (race-around). The M-S design splits capturing (CLK=1) from outputting (CLK=0), ensuring exactly one transition per clock pulse.
Two-Phase Operation
The Master samples inputs when CLK is HIGH, storing them internally in Qm. When CLK goes LOW, the Slave copies Qm to Q — the output changes only on the falling edge.
Modern Alternative
Modern ICs use true edge-triggering (propagation delay-based) instead of Master-Slave, providing even more reliable single-edge operation used in all CMOS logic families today.